f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1
f "c:\prj\example-4-13\ram_basic\ram_basic.v"; #file 2
VNAME 'work.ram_basic.verilog'; # view id 0
@EuyRsFCDN88CRsbN0
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:11:06 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:54:03 2008
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:12:41 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 11:28:48 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:44:06 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:44:06 2008
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:35:19 2008
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
