-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:12:41 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY cc IS
END cc;
ARCHITECTURE testbench_arch OF cc IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT hour1
PORT (
clkh : In std_logic;
reset : In std_logic;
Hour1 : Buffer std_logic_vector (3 DOWNTO 0);
hour2 : Buffer std_logic_vector (3 DOWNTO 0)
);
END COMPONENT;
SIGNAL clkh : std_logic;
SIGNAL reset : std_logic;
SIGNAL Hour1 : std_logic_vector (3 DOWNTO 0);
SIGNAL hour2 : std_logic_vector (3 DOWNTO 0);
BEGIN
UUT : hour1
PORT MAP (
clkh => clkh,
reset => reset,
Hour1 => Hour1,
hour2 => hour2
);
PROCESS -- clock process for clkh,
BEGIN
CLOCK_LOOP : LOOP
clkh WAIT FOR 10 ns;
clkh WAIT FOR 10 ns;
WAIT FOR 40 ns;
clkh WAIT FOR 40 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Process for clkh
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_Hour1(
next_Hour1 : std_logic_vector (3 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (Hour1 /= next_Hour1) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns Hour1="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Hour1);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Hour1);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_hour2(
next_hour2 : std_logic_vector (3 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (hour2 /= next_hour2) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns hour2="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, hour2);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_hour2);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- --------------------
reset -- --------------------
WAIT FOR 200 ns; -- Time=200 ns
reset -- --------------------
WAIT FOR 8060 ns; -- Time=8260 ns
-- --------------------
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected. "
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT, string'(
" errors found in simulation"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
CONFIGURATION hour1_cfg OF cc IS
FOR testbench_arch
END FOR;
END hour1_cfg;
