设计与验证verilog hdl
源代码在线查看： ram_basic.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1
f "c:\prj\example-4-13\ram_basic\ram_basic.v"; #file 2
VNAME 'work.ram_basic.verilog'; # view id 0
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s@:@.U6:4:.U:.-Rf.cnUd66cnn:.U6cdcR6neaQ) mXRARzwuv)QR08NNk_F0L_FknVr9m
S=08NNk_F09rn
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S=08NNk_F09r6
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s@:@.U6:4:.U:.-Rf.cnUd66cnn:.U6cdcR6neaQ) mXRARzwuv)QR08NNk_F0L_FkcVr9m
S=08NNk_F09rc
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s@:@.U6:4:.U:.-Rf.cnUd66cnn:.U6cdcR6neaQ) mXRARzwuv)QR08NNk_F0L_FkdVr9m
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c9S=q6Ns88_6Or97
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