-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:11:06 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY b IS
END b;
ARCHITECTURE testbench_arch OF b IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT minute1
PORT (
clkm : In std_logic;
reset : In std_logic;
Min1 : Buffer std_logic_vector (3 DOWNTO 0);
Min2 : Buffer std_logic_vector (3 DOWNTO 0);
Enmin : Out std_logic
);
END COMPONENT;
SIGNAL clkm : std_logic;
SIGNAL reset : std_logic;
SIGNAL Min1 : std_logic_vector (3 DOWNTO 0);
SIGNAL Min2 : std_logic_vector (3 DOWNTO 0);
SIGNAL Enmin : std_logic;
BEGIN
UUT : minute1
PORT MAP (
clkm => clkm,
reset => reset,
Min1 => Min1,
Min2 => Min2,
Enmin => Enmin
);
PROCESS -- clock process for clkm,
BEGIN
CLOCK_LOOP : LOOP
clkm WAIT FOR 10 ns;
clkm WAIT FOR 10 ns;
WAIT FOR 40 ns;
clkm WAIT FOR 40 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Process for clkm
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_Enmin(
next_Enmin : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (Enmin /= next_Enmin) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns Enmin="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Enmin);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Enmin);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_Min1(
next_Min1 : std_logic_vector (3 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (Min1 /= next_Min1) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns Min1="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Min1);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Min1);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_Min2(
next_Min2 : std_logic_vector (3 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (Min2 /= next_Min2) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns Min2="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Min2);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Min2);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- --------------------
reset -- --------------------
WAIT FOR 200 ns; -- Time=200 ns
reset -- --------------------
WAIT FOR 6060 ns; -- Time=6260 ns
-- --------------------
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected. "
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT, string'(
" errors found in simulation"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
CONFIGURATION minute1_cfg OF b IS
FOR testbench_arch
END FOR;
END minute1_cfg;
