f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\stratix.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #fil
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 1
f "c:\prj\fsm_abc\state2\state2.v"; #file 2
VNAME 'work.state2.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssNH
C#uaq)RO
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 1
f "c:\prj\fsm_abc\state1\state1.v"; #file 2
VNAME 'work.state1.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssNH
C#uaq)RO
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2
f "c:\prj\fsm_abc\state1\state1.v"; #file 3
VNAME 'LUCENT.OB.PRIM'; # view id 0
VNAME 'LUCENT.IB.PRI
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 1
f "c:\prj\fsm_abc\state3\state3.v"; #file 2
VNAME 'work.state2.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssNH
C#uaq)RO
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2
f "c:\prj\fsm_abc\state3\state3.v"; #file 3
VNAME 'LUCENT.OB.PRIM'; # view id 0
VNAME 'LUCENT.IB.PRI
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2
f "c:\prj\fsm_abc\state_default\state2_default.v"; #file 3
VNAME 'LUCENT.VLO.PRIM'; # view id 0
VNAM
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 1
f "c:\prj\fsm_abc\state_default\state2_default.v"; #file 2
VNAME 'work.state2_default.verilog'; # view id 0
@EuyRsFCDN88C
