f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1
f "c:\prj\example-4-1\reg_counter.v"; #file 2
VNAME 'work.reg_counter.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssN
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\xp.v"; #file 2
f "c:\prj\example-4-9\asyn_rst\asyn_rst.v"; #file 3
VNAME 'LUCENT.VLO.PRIM'; # view id 0
VNAME 'LUCE
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\lucent\xp.v"; #file 1
f "c:\prj\example-4-9\asyn_rst\asyn_rst.v"; #file 2
VNAME 'work.asyn_rst.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssNH
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\xp.v"; #file 2
f "c:\prj\example-4-9\syn_rst\syn_rst.v"; #file 3
VNAME 'LUCENT.VHI.PRIM'; # view id 0
VNAME 'LUCENT
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\lucent\xp.v"; #file 1
f "c:\prj\example-4-9\syn_rst\syn_rst.v"; #file 2
VNAME 'work.syn_rst.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssNH
C
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1
f "c:\prj\example-4-8\srl2pal.v"; #file 2
VNAME 'work.srl2pal.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssNH
C#uaq
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\cyclone.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #fil
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\cyclone.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #fil
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1
f "c:\prj\example-4-5\mux.v"; #file 2
VNAME 'work.mux.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssNH
C#uaq)RO"Gdj#
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 1
f "c:\prj\example-4-5\mux.v"; #file 2
VNAME 'work.mux.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssNH
C#uaq)RO"Gdj#60cJ
