设计与验证verilog hdl
源代码在线查看： reg_counter.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1
f "c:\prj\example-4-1\reg_counter.v"; #file 2
VNAME 'work.reg_counter.verilog'; # view id 0
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