设计与验证verilog hdl
源代码在线查看： state2_default.srm
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2
f "c:\prj\fsm_abc\state_default\state2_default.v"; #file 3
VNAME 'LUCENT.VLO.PRIM'; # view id 0
VNAME 'LUCENT.OB.PRIM'; # view id 1
VNAME 'LUCENT.IB.PRIM'; # view id 2
VNAME 'LUCENT.FD1S3AX.PRIM'; # view id 3
VNAME 'work.state2_default.verilog'; # view id 4
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