f "noname"; #file 0
f "d:\prj_d\example-s1-1\fht_example\before_optimized\fht_unit1.v"; #file 1
f "d:\prj_d\example-s1-1\fht_example\before_optimized\fht_unit2.v"; #file 2
f "d:\prj_d\example-s1-1\
f "noname"; #file 0
f "c:\program files\synplicity\synplify_73\lib\vhd\std.vhd"; #file 1
f "d:\924lyj\924\generator_sin.vhd"; #file 2
f "c:\program files\synplicity\synplify_73\lib\vhd\std1164.vhd"
f "noname"; #file 0
f "c:\synplicity\synplify_70\lib\vhd\std.vhd"; #file 1
f "h:\can\cpld\rev_1\control.vhd"; #file 2
f "c:\synplicity\synplify_70\lib\vhd\std1164.vhd"; #file 3
f "c:\synplicity\sy
f "noname"; #file 0
f "c:\libero\synplify\synplify_88a1\lib\proasic\proasic3.v"; #file 1
f "h:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v"; #file 2
f "h:\fpga_test\fpga_
f "noname"; #file 0
f "d:\isptools5_1\synpbase\lib\lucent\machxo.v"; #file 1
f "d:\isptools5_1\ispcpld\generic\verilog\synplify\generic.v"; #file 2
f "d:\isptools5_1\ispcpld\..\cae_library\synthesi
f "noname"; #file 0
f "noname"; #file 1
f "d:\isptools5_1\synpbase\lib\lucent\machxo.v"; #file 2
f "d:\isptools5_1\ispcpld\generic\verilog\synplify\generic.v"; #file 3
f "d:\isptools5_1\ispcpld\..
f "noname"; #file 0
f "c:\libero\synplify\synplify_85f\lib\vhd\std.vhd"; #file 1
f "c:\libero\synplify\synplify_85f\lib\proasic\proasic3.vhd"; #file 2
f "c:\libero\synplify\synplify_85f\lib\vhd\std
