f "noname"; #file 0
f "d:\prj_d\synplify_pro\source\verilog\alu.v"; #file 1
f "d:\prj_d\synplify_pro\source\verilog\hdl_demo.v"; #file 2
VNAME 'work.alu.verilog'; # view id 0
VNAME 'work.hdl_demo.
f "noname"; #file 0
f "j:\eda\synplicity\synplify_70\bin\..\lib\xilinx\virtex2p.v"; #file 1
f "j:\projects\ise\coregendemo\dpram_core_demo\dpram_core.v"; #file 2
f "j:\projects\ise\coregendemo\dpra
f "noname"; #file 0
f "d:\cd\example-8-2\synplify_syn\module_b.v"; #file 1
f "d:\cd\example-8-2\synplify_syn\module_c.v"; #file 2
f "d:\cd\example-8-2\synplify_syn\module_a.v"; #file 3
f "d:\cd\ex
f "noname"; #file 0
f "d:\cd\example-8-2\synplify_syn\module_b.v"; #file 1
f "d:\cd\example-8-2\synplify_syn\module_c.v"; #file 2
f "d:\cd\example-8-2\synplify_syn\module_a.v"; #file 3
f "d:\cd\ex
