module mux (en, a, b, mux_out); input en; input a, b; output mux_out; wire mux_out; assign mux_out = (en)? a : b; endmodule
http://www.codebf.com/read/14659/401053
`timescale 1ns/1ps module clk_div_phase_tb; reg clk_200K; reg rst; wire clk_100K, clk_50K, clk_25K; initial begin rst = 0; clk_200K = 0; # 10;
http://www.codebf.com/read/14659/401055
module clk_div_phase (rst, clk_200K, clk_100K, clk_50K, clk_25K); input clk_200K; input rst; output clk_100K, clk_50K, clk_25K; wire clk_100K, clk_50K, clk_25K; re
http://www.codebf.com/read/14659/401072
module clk_3div (clk,reset,clk_out); input clk, reset; output clk_out; reg[1:0] state; reg clk1; always @(posedge clk or negedge reset) if(!reset) state
http://www.codebf.com/read/14659/401086
`timescale 1ns/1ps module clk_3div_tb; reg clk; reg rst_; wire clk_3div; initial begin rst_ = 0; clk = 0; # 10; rst_ = 1; # 1000;
http://www.codebf.com/read/14659/401108
module decode_cmb2 (addr, CS, cs1, cs2, cs3, cs4); input [7:0] addr; // only the 2 MSB bits used input CS; // Low effect output cs1, cs2, cs3, cs4; // Low effect wire cs1,
http://www.codebf.com/read/14659/401129
`timescale 1ns/100ps module decode_cmb_tb; reg [7:0] addr; // only the 2 MSB bits used reg CS; // Low effect wire cs1a, cs2a, cs3a, cs4a; // Low effect wire cs1b, cs2b, cs3b
http://www.codebf.com/read/14659/401130
http://www.codebf.com/read/14659/401131
module decode_cmb (addr, CS, cs1, cs2, cs3, cs4); input [7:0] addr; // only the 2 MSB bits used input CS; // Low effect output cs1, cs2, cs3, cs4; // Low effect reg cs1, cs
http://www.codebf.com/read/14659/401132
http://www.codebf.com/read/14659/401145
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