module HalfAdd (X, Y, SUM, C_out);//半加器模块
input X;
input Y;
output SUM;
output C_out;
assign SUM = X ^ Y ;
assign C_out = X & Y ;
endmodule
module FullAdd (X, Y, C_in, SUM, C_out);//全加器模块
i
module mux (en, a, b, c, d, mux_out);
input [1:0] en;
input a, b, c, d;
output mux_out;
reg mux_out;
always @ (en or a or b or c or d)
case(en)
2'b00: mux_ou
module mux (en, a, b, c, d, mux_out);
input [1:0] en;
input a, b, c, d;
output mux_out;
reg mux_out;
always @ (en or a or b or c or d)
case(en)
2'b00: mux_ou
