-
v=0
o=- 49451 3 IN IP4 127.0.0.1
s=Test MPEG Video session
i=Parameters for the session streamed by "testMPEG1or2VideoStreamer"
t=0 0
a=tool:testMPEG1or2VideoStreamer
a=type:broadcast
m=video 8888 RTP
http://www.codebf.com/read/14231/323539
-
v=0
o=- 49452 4 IN IP4 127.0.0.1
s=Test MP3 session
i=Parameters for the session streamed by "testMP3Streamer"
t=0 0
a=tool:testMP3Streamer
a=type:broadcast
m=audio 6666 RTP/AVP 14
c=IN IP4 239.255.42
http://www.codebf.com/read/14231/323544
-
module mod_copy1 (sel, a, b, c, d, data_out);
input sel, a, b, c, d;
output data_out;
assign data_out= (sel)? (a+b) : (c+d) ;
endmodule
http://www.codebf.com/read/14659/400656
-
module mod_copy1 (sel, a, b, c, d, data_out);
input sel, a, b, c, d;
output data_out;
wire temp1, temp2;
assign temp1 = (sel)? (a) : (c) ;
assign temp2 = (sel)? (b) : (d) ;
assign data_out = t
http://www.codebf.com/read/14659/400657
-
// synchronous write by cpu clock, use my_wr as condition
module write_reg (rst, data_in, my_wr, CS_reg1, CS_reg2, CS_reg3, reg1, reg2, reg3);
input rst, my_wr, CS_reg1, CS_reg2, CS_reg3;
http://www.codebf.com/read/14659/400696
-
// synchronous write by cpu clock, use my_wr as condition
module read_reg (rst, data_out, my_rd, CS_reg1, CS_reg2, CS_reg3, reg1, reg2, reg3);
input rst, my_rd, CS_reg1, CS_reg2, CS_reg3;
http://www.codebf.com/read/14659/400697
-
module top (rst, CS_, OE_, WR_, Addr, data_bus);
input rst;
input CS_, OE_, WR_;
input [7:0] Addr;
inout [7:0] data_bus;
wire [7:0] data_in;
wire [7:0] data_out;
wire my_
http://www.codebf.com/read/14659/400698
-
// decode circuit, combination logic
module decode (CS_, OE_, WR_, Addr, my_wr, my_rd, CS_reg1, CS_reg2, CS_reg3);
input CS_, OE_, WR_;
input [7:0] Addr;
output my_wr, my_rd;
http://www.codebf.com/read/14659/400699
-
// synchronous write by cpu clock, use my_wr as condition
module write_reg (OE_, rst, data_in, my_wr, CS_reg1, CS_reg2, CS_reg3, reg1, reg2, reg3);
input OE_, rst, my_wr, CS_reg1, CS_reg2,
http://www.codebf.com/read/14659/400714
-
// synchronous write by cpu clock, use my_wr as condition
module read_reg (OE_, rst, data_out, my_rd, CS_reg1, CS_reg2, CS_reg3, reg1, reg2, reg3);
input OE_, rst, my_rd, CS_reg1, CS_reg2,
http://www.codebf.com/read/14659/400715
