-
module wch_fht(Clk,Reset,
PreFhtStar,
In0,In1,In2,In3,In4,In5,In6,In7,
In8,In9,In10,In11,In12,In13,In14,In15,
Out0,Out1,Out2,Out3,Out4,Out5,Out6,Out7,Ou
http://www.codebf.com/read/14659/401176
-
/************************************************************************/
/* Fast Hadamard */
/***********************************************
http://www.codebf.com/read/14659/401181
-
/************************************************************************/
/* Fast Hadamard */
/***********************************************
http://www.codebf.com/read/14659/401184
-
module fhtpart(Clk,Reset,FhtStarOne,FhtStarTwo,FhtStarThree,FhtStarFour,
I0,I1,I2,I3,I4,I5,I6,I7,I8,
I9,I10,I11,I12,I13,I14,I15,
Out0,Out1,Out2,Out3,Out4,Out5,Out6,
http://www.codebf.com/read/14659/401199
-
/************************************************************************/
/* Fast Hadamard */
/***********************************************
http://www.codebf.com/read/14659/401200
-
/************************************************************************/
/* Fast Hadamard */
/***********************************************
http://www.codebf.com/read/14659/401201
-
module HalfAdd (X, Y, SUM, C_out);//半加器模块
input X;
input Y;
output SUM;
output C_out;
//assign SUM = X ^ Y ;
//assign C_out = X & Y ;
xor u_xor (SUM, X, Y); //门级原语实例
and u_and (C_out, X, Y); /
http://www.codebf.com/read/14659/401205
-
`timescale 1ns/100ps
module TB ;
reg Ck, Rst_n, Din;
wire Dout;
//Clock generation
initial
begin
Ck = 0;
forever
Ck = #10 ~ Ck;
end
//Reset generation
initial
begin
http://www.codebf.com/read/14659/401208
-
module single_if(a, b, c, d, sel0, sel1, sel2, sel3, z);
input a, b, c, d;
input sel0, sel1, sel2, sel3;
output z;
reg z;
always @(a or b or c or d or sel0 or sel1 or sel2 or sel3)
begin
http://www.codebf.com/read/14659/401209
-
// Use case statement to build decode circuit without prior
`timescale 1ns/1ps
module if_single_decode (addr_H, CS1, CS2, CS3, CS4);
input [2:0] addr_H;
output CS1, CS2, CS3, CS4;
reg
http://www.codebf.com/read/14659/401263
