Verilog编写的UART程序源代码。测试成功。支持字符串发送
源代码在线查看： uart.flow.rpt
Flow report for uart
Sun Apr 05 21:29:19 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-----------------------------------------+
; Flow Status ; Successful - Sun Apr 05 21:29:18 2009 ;
; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Web Edition ;
; Revision Name ; uart ;
; Top-level Entity Name ; my_uart_top ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 498 / 8,256 ( 6 % ) ;
; Total combinational functions ; 362 / 8,256 ( 4 % ) ;
; Dedicated logic registers ; 376 / 8,256 ( 5 % ) ;
; Total registers ; 376 ;
; Total pins ; 8 / 138 ( 6 % ) ;
; Total virtual pins ; 3 ;
; Total memory bits ; 384 / 165,888 ( < 1 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+-----------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/18/2009 19:31:26 ;
; Main task ; Compilation ;
; Revision Name ; uart ;
+-------------------+---------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------------------------+---------------+-------------+------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------------------------+---------------+-------------+------------------+
; COMPILER_SIGNATURE_ID ; 146461944111.123737588600680 ; -- ; -- ; -- ;
; ENABLE_SIGNALTAP ; On ; -- ; -- ; -- ;
; PARTITION_COLOR ; 14622752 ; -- ; my_uart_top ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; my_uart_top ; Top ;
; SLD_NODE_CREATOR_ID ; 110 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_ENTITY_NAME ; sld_signaltap ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_DATA_BITS=3 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_BITS=3 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_INFO=805334528 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_POWER_UP_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK=000000000000000000000000000000 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK_LENGTH=30 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SEGMENT_SIZE=128 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ATTRIBUTE_MEM_MODE=OFF ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_FLOW_USE_GENERATED=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_BITS=11 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_BUFFER_FULL_STOP=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_CURRENT_RESOURCE_WIDTH=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_CRC_LOWORD=55548 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_CRC_HIWORD=30383 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SAMPLE_DEPTH=128 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_IN_ENABLED=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ADVANCED_TRIGGER_ENTITY=basic,1, ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL_PIPELINE=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ENABLE_ADVANCED_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
; TOP_LEVEL_ENTITY ; my_uart_top ; uart ; -- ; -- ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_palace ;
; USE_SIGNALTAP_FILE ; stp1.stp ; -- ; -- ; -- ;
+------------------------------------+---------------------------------------------------+---------------+-------------+------------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:25 ; 1.0 ; 191 MB ; 00:00:09 ;
; Fitter ; 00:00:08 ; 1.0 ; 177 MB ; 00:00:05 ;
; Assembler ; 00:00:08 ; 1.0 ; 154 MB ; 00:00:02 ;
; Classic Timing Analyzer ; 00:00:04 ; 1.0 ; 115 MB ; 00:00:01 ;
; Analysis & Synthesis ; 00:00:18 ; 1.0 ; 191 MB ; 00:00:08 ;
; Partition Merge ; 00:00:06 ; 1.0 ; 166 MB ; 00:00:01 ;
; Fitter ; 00:00:06 ; 1.0 ; 177 MB ; 00:00:05 ;
; Assembler ; 00:00:06 ; 1.0 ; 154 MB ; 00:00:01 ;
; Classic Timing Analyzer ; 00:00:02 ; 1.0 ; 115 MB ; 00:00:01 ;
; Analysis & Synthesis ; 00:00:22 ; 1.0 ; 196 MB ; 00:00:10 ;
; Partition Merge ; 00:00:06 ; 1.0 ; 171 MB ; 00:00:02 ;
; Fitter ; 00:00:05 ; 1.0 ; 182 MB ; 00:00:05 ;
; Assembler ; 00:00:06 ; 1.0 ; 158 MB ; 00:00:02 ;
; Classic Timing Analyzer ; 00:00:02 ; 1.0 ; 119 MB ; 00:00:01 ;
; Analysis & Synthesis ; 00:00:17 ; 1.0 ; 196 MB ; 00:00:09 ;
; Partition Merge ; 00:00:06 ; 1.0 ; 171 MB ; 00:00:02 ;
; Fitter ; 00:00:06 ; 1.0 ; 182 MB ; 00:00:05 ;
; Assembler ; 00:00:06 ; 1.0 ; 158 MB ; 00:00:02 ;
; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 119 MB ; 00:00:01 ;
; Total ; 00:02:40 ; -- ; -- ; 00:01:12 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart
quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart
quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only
quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
quartus_cdb --read_settings_files=off --write_settings_files=off uart -c uart --merge=on
quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart
quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart
quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only
quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
quartus_cdb --read_settings_files=off --write_settings_files=off uart -c uart --merge=on
quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart
quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart
quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only
quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
quartus_cdb --read_settings_files=off --write_settings_files=off uart -c uart --merge=on
quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart
quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart
quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only
