一个完整的用cpld实现串口功能的代码。经过验证

源代码在线查看: uart.flow.rpt

软件大小: 56 K
上传用户: dongchenxi2
关键词: cpld 串口 代码
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相关代码

				Flow report for UART
				Sat Feb 18 12:32:23 2006
				Version 5.0 Build 148 04/26/2005 SJ Full Version
				
				
				---------------------
				; Table of Contents ;
				---------------------
				  1. Legal Notice
				  2. Flow Summary
				  3. Flow Settings
				  4. Flow Elapsed Time
				  5. Flow Log
				
				
				
				----------------
				; Legal Notice ;
				----------------
				Copyright (C) 1991-2005 Altera Corporation
				Your use of Altera Corporation's design tools, logic functions 
				and other software and tools, and its AMPP partner logic       
				functions, and any output files any of the foregoing           
				(including device programming or simulation files), and any    
				associated documentation or information are expressly subject  
				to the terms and conditions of the Altera Program License      
				Subscription Agreement, Altera MegaCore Function License       
				Agreement, or other applicable license agreement, including,   
				without limitation, that your use is for the sole purpose of   
				programming logic devices manufactured by Altera and sold by   
				Altera or its authorized distributors.  Please refer to the    
				applicable agreement for further details.
				
				
				
				+--------------------------------------------------------------------+
				; Flow Summary                                                       ;
				+-------------------------+------------------------------------------+
				; Flow Status             ; Successful - Sat Feb 18 12:32:23 2006    ;
				; Quartus II Version      ; 5.0 Build 148 04/26/2005 SJ Full Version ;
				; Revision Name           ; UART                                     ;
				; Top-level Entity Name   ; UART                                     ;
				; Family                  ; MAX II                                   ;
				; Device                  ; EPM1270T144C5                            ;
				; Timing Models           ; Final                                    ;
				; Met timing requirements ; No                                       ;
				; Total logic elements    ; 195 / 1,270 ( 15 % )                     ;
				; Total pins              ; 14 / 116 ( 12 % )                        ;
				; Total virtual pins      ; 0                                        ;
				; UFM blocks              ; 0 / 1 ( 0 % )                            ;
				+-------------------------+------------------------------------------+
				
				
				+-----------------------------------------+
				; Flow Settings                           ;
				+-------------------+---------------------+
				; Option            ; Setting             ;
				+-------------------+---------------------+
				; Start date & time ; 02/18/2006 12:31:59 ;
				; Main task         ; Compilation         ;
				; Revision Name     ; UART                ;
				+-------------------+---------------------+
				
				
				+-------------------------------------+
				; Flow Elapsed Time                   ;
				+----------------------+--------------+
				; Module Name          ; Elapsed Time ;
				+----------------------+--------------+
				; Analysis & Synthesis ; 00:00:08     ;
				; Fitter               ; 00:00:08     ;
				; Assembler            ; 00:00:00     ;
				; Timing Analyzer      ; 00:00:03     ;
				; Total                ; 00:00:19     ;
				+----------------------+--------------+
				
				
				------------
				; Flow Log ;
				------------
				quartus_map --read_settings_files=on --write_settings_files=off UART -c UART
				quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART
				quartus_asm --read_settings_files=off --write_settings_files=off UART -c UART
				quartus_tan --read_settings_files=off --write_settings_files=off UART -c UART
				
				
				
							

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