通用穿行通信控制器

源代码在线查看: uart.flow.rpt

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关键词: 通信控制器
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相关代码

				Flow report for uart
				Fri Jun 18 16:43:26 2004
				Version 4.0 Build 190 1/28/2004 SJ Full Version
				
				
				---------------------
				; Table of Contents ;
				---------------------
				  1. Legal Notice
				  2. Flow Summary
				  3. Flow Settings
				  4. Flow Elapsed Time
				  5. Flow Log
				
				
				
				----------------
				; Legal Notice ;
				----------------
				Copyright (C) 1991-2004 Altera Corporation
				Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
				support information,  device programming or simulation file,  and any other
				associated  documentation or information  provided by  Altera  or a partner
				under  Altera's   Megafunction   Partnership   Program  may  be  used  only
				to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
				other  use  of such  megafunction  design,  netlist,  support  information,
				device programming or simulation file,  or any other  related documentation
				or information  is prohibited  for  any  other purpose,  including, but not
				limited to  modification,  reverse engineering,  de-compiling, or use  with
				any other  silicon devices,  unless such use is  explicitly  licensed under
				a separate agreement with  Altera  or a megafunction partner.  Title to the
				intellectual property,  including patents,  copyrights,  trademarks,  trade
				secrets,  or maskworks,  embodied in any such megafunction design, netlist,
				support  information,  device programming or simulation file,  or any other
				related documentation or information provided by  Altera  or a megafunction
				partner, remains with Altera, the megafunction partner, or their respective
				licensors. No other licenses, including any licenses needed under any third
				party's intellectual property, are provided herein.
				
				
				
				+---------------------------------------------------------------+
				; Flow Summary                                                  ;
				+-----------------------+---------------------------------------+
				; Flow Status           ; Successful - Fri Jun 18 16:43:26 2004 ;
				; Revision Name         ; uart                                  ;
				; Top-level Entity Name ; uart                                  ;
				; Family                ; Cyclone                               ;
				; Device                ; EP1C20F400C8                          ;
				; Total logic elements  ; 147                                   ;
				; Total pins            ; 65                                    ;
				; Total memory bits     ; 0                                     ;
				; Total PLLs            ; 0                                     ;
				+-----------------------+---------------------------------------+
				
				
				+-----------------------------------------+
				; Flow Settings                           ;
				+------------------------------------------
				; Option            ; Setting             ;
				+-------------------+---------------------+
				; Start date & time ; 06/18/2004 16:43:17 ;
				; Main task         ; Compilation         ;
				; Revision Name     ; uart                ;
				+-------------------+---------------------+
				
				
				+-------------------------------------+
				; Flow Elapsed Time                   ;
				+--------------------------------------
				; Module Name          ; Elapsed Time ;
				+----------------------+--------------+
				; Analysis & Synthesis ; 00:00:08     ;
				; Total                ; 00:00:08     ;
				+----------------------+--------------+
				
				
				------------
				; Flow Log ;
				------------
				quartus_map --import_settings_files=on --export_settings_files=off uart -c uart
				
				
				
							

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