利用图元实现层次化设计,编程完成数字序列的乘积求和

源代码在线查看: function.flow.rpt

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关键词: 编程 数字序列
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相关代码

				Flow report for function
				Thu Apr 02 09:22:41 2009
				Version 6.0 Build 178 04/27/2006 SJ Full Version
				
				
				---------------------
				; Table of Contents ;
				---------------------
				  1. Legal Notice
				  2. Flow Summary
				  3. Flow Settings
				  4. Flow Non-Default Global Settings
				  5. Flow Elapsed Time
				  6. Flow Log
				
				
				
				----------------
				; Legal Notice ;
				----------------
				Copyright (C) 1991-2006 Altera Corporation
				Your use of Altera Corporation's design tools, logic functions 
				and other software and tools, and its AMPP partner logic 
				functions, and any output files any of the foregoing 
				(including device programming or simulation files), and any 
				associated documentation or information are expressly subject 
				to the terms and conditions of the Altera Program License 
				Subscription Agreement, Altera MegaCore Function License 
				Agreement, or other applicable license agreement, including, 
				without limitation, that your use is for the sole purpose of 
				programming logic devices manufactured by Altera and sold by 
				Altera or its authorized distributors.  Please refer to the 
				applicable agreement for further details.
				
				
				
				+-------------------------------------------------------------------------------+
				; Flow Summary                                                                  ;
				+------------------------------------+------------------------------------------+
				; Flow Status                        ; Successful - Thu Apr 02 09:22:41 2009    ;
				; Quartus II Version                 ; 6.0 Build 178 04/27/2006 SJ Full Version ;
				; Revision Name                      ; function                                 ;
				; Top-level Entity Name              ; Block1                                   ;
				; Family                             ; Cyclone II                               ;
				; Met timing requirements            ; Yes                                      ;
				; Total logic elements               ; 49 / 4,608 ( 1 % )                       ;
				; Total registers                    ; 37                                       ;
				; Total pins                         ; 37 / 89 ( 42 % )                         ;
				; Total virtual pins                 ; 0                                        ;
				; Total memory bits                  ; 0 / 119,808 ( 0 % )                      ;
				; Embedded Multiplier 9-bit elements ; 1 / 26 ( 4 % )                           ;
				; Total PLLs                         ; 0 / 2 ( 0 % )                            ;
				; Device                             ; EP2C5T144C6                              ;
				; Timing Models                      ; Final                                    ;
				+------------------------------------+------------------------------------------+
				
				
				+-----------------------------------------+
				; Flow Settings                           ;
				+-------------------+---------------------+
				; Option            ; Setting             ;
				+-------------------+---------------------+
				; Start date & time ; 04/02/2009 09:22:27 ;
				; Main task         ; Compilation         ;
				; Revision Name     ; function            ;
				+-------------------+---------------------+
				
				
				+----------------------------------------------------------------------+
				; Flow Non-Default Global Settings                                     ;
				+------------------+--------+---------------+-------------+------------+
				; Assignment Name  ; Value  ; Default Value ; Entity Name ; Section Id ;
				+------------------+--------+---------------+-------------+------------+
				; TOP_LEVEL_ENTITY ; Block1 ; function      ; --          ; --         ;
				+------------------+--------+---------------+-------------+------------+
				
				
				+-------------------------------------+
				; Flow Elapsed Time                   ;
				+----------------------+--------------+
				; Module Name          ; Elapsed Time ;
				+----------------------+--------------+
				; Analysis & Synthesis ; 00:00:04     ;
				; Fitter               ; 00:00:03     ;
				; Assembler            ; 00:00:03     ;
				; Timing Analyzer      ; 00:00:01     ;
				; Total                ; 00:00:11     ;
				+----------------------+--------------+
				
				
				------------
				; Flow Log ;
				------------
				quartus_map --read_settings_files=on --write_settings_files=off function -c function
				quartus_fit --read_settings_files=off --write_settings_files=off function -c function
				quartus_asm --read_settings_files=off --write_settings_files=off function -c function
				quartus_tan --read_settings_files=off --write_settings_files=off function -c function --timing_analysis_only
				
				
				
							

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