Flow report for uart
Thu May 07 23:21:58 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------+
; Flow Summary ;
+--------------------------+------------------------------------------+
; Flow Status ; Successful - Thu May 07 23:21:58 2009 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; uart ;
; Top-level Entity Name ; top ;
; Family ; Cyclone ;
; Device ; EP1C3T144C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 215 / 2,910 ( 7 % ) ;
; Total pins ; 25 / 104 ( 24 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 59,904 ( 0 % ) ;
; DSP block 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; 0 / 1 ( 0 % ) ;
; Total DLLs ; N/A until Partition Merge ;
+--------------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 05/07/2009 23:21:40 ;
; Main task ; Compilation ;
; Revision Name ; uart ;
+-------------------+---------------------+
+-----------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------+---------------+-------------+------------+
; PARTITION_COLOR ; 2147039 ; -- ; top ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; top ; Top ;
; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;
; TOP_LEVEL_ENTITY ; top ; uart ; -- ; -- ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_palace ;
+------------------------------------+---------+---------------+-------------+------------+
+------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ;
+-------------------------+--------------+-------------------------+
; Analysis & Synthesis ; 00:00:06 ; 1.0 ;
; Fitter ; 00:00:05 ; 1.0 ;
; Assembler ; 00:00:02 ; 1.0 ;
; Classic Timing Analyzer ; 00:00:01 ; 1.0 ;
; Total ; 00:00:14 ; -- ;
+-------------------------+--------------+-------------------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart
quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart
quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only
