-- VHDL Instantiation Created from source file mux2.vhd -- 00:32:58 03/08/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT mux2
PORT(
d0 : IN std_logic_vector(8 downto 0);
d1 : IN std_logic_vector(8 downto 0);
s : IN std_logic;
o : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
Inst_mux2: mux2 PORT MAP(
d0 => ,
d1 => ,
s => ,
o =>
);