《CPLDFPGA嵌入式应用开发技术白金手册》源代码

				--mux2
				library IEEE;
				use IEEE.std_logic_1164.all;
				use IEEE.std_logic_unsigned.all;
				use IEEE.std_logic_arith.all;
				entity mux2 is
				 port(a,b,en:in std_logic;
				        y:out std_logic);
				 end mux2;
				architecture behav of mux2 is
				begin
				y				end behav;