用vhdl硬件语言设计的16位cpu

				-- mux2.vhd
				
				-- This module implements a 2-to-1 multiplexor for ALU
				
				-- Inputs: 
				--    A, B        - 16-bit mux inputs 
				--    Sel         - 1-bit Select for mux 
				
				-- Outputs: 
				--    Z           - 16-bit mux output
				
				-- Author:    Easyright
				-- E-mail:    support@easyright.net
				-- Date:      17-08-2003
				-- Copyright: http://www.EasyRight.net
				
				------------------------------------------------------------------------------------------------------ 
				
				library ieee;
				use ieee.std_logic_1164.all;
				use ieee.std_logic_unsigned.all;
				
				entity mux2 is
				  port (
				    Sel:  in std_logic;
				    A, B: in std_logic_vector(15 downto 0);
				    Z:    out std_logic_vector(15 downto 0)
				  );
				end mux2;
				
				architecture arc_mux2 of mux2 is
				begin 
				  with Sel select 
				    Z 				         B when '1', 
				         A when others;
				end arc_mux2;