Xiliunx公司Spart3板子与cc2420通信源码

源代码在线查看: transceiver.flow.rpt

软件大小: 26 K
上传用户: saas1988
关键词: Xiliunx Spart3 2420 cc
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相关代码

				Flow report for transceiver
				Thu Nov 13 21:05:32 2008
				Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
				
				
				---------------------
				; Table of Contents ;
				---------------------
				  1. Legal Notice
				  2. Flow Summary
				  3. Flow Settings
				  4. Flow Non-Default Global Settings
				  5. Flow Elapsed Time
				  6. Flow Log
				
				
				
				----------------
				; Legal Notice ;
				----------------
				Copyright (C) 1991-2007 Altera Corporation
				Your use of Altera Corporation's design tools, logic functions 
				and other software and tools, and its AMPP partner logic 
				functions, and any output files from any of the foregoing 
				(including device programming or simulation files), and any 
				associated documentation or information are expressly subject 
				to the terms and conditions of the Altera Program License 
				Subscription Agreement, Altera MegaCore Function License 
				Agreement, or other applicable license agreement, including, 
				without limitation, that your use is for the sole purpose of 
				programming logic devices manufactured by Altera and sold by 
				Altera or its authorized distributors.  Please refer to the 
				applicable agreement for further details.
				
				
				
				+--------------------------------------------------------------------------+
				; Flow Summary                                                             ;
				+-------------------------------+------------------------------------------+
				; Flow Status                   ; Flow Failed - Thu Nov 13 21:05:32 2008   ;
				; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Full Version ;
				; Revision Name                 ; transceiver                              ;
				; Top-level Entity Name         ; transceiver                              ;
				; Family                        ; Stratix II                               ;
				; Met timing requirements       ; N/A                                      ;
				; Logic utilization             ; N/A until Partition Merge                ;
				;     Combinational ALUTs       ; N/A until Partition Merge                ;
				;     Dedicated logic registers ; N/A until Partition Merge                ;
				; Total registers               ; N/A until Partition Merge                ;
				; Total pins                    ; N/A until Partition Merge                ;
				; Total virtual pins            ; N/A until Partition Merge                ;
				; Total block memory bits       ; N/A until Partition Merge                ;
				; DSP block 9-bit elements      ; N/A until Partition Merge                ;
				; Total PLLs                    ; N/A until Partition Merge                ;
				; Total DLLs                    ; N/A until Partition Merge                ;
				+-------------------------------+------------------------------------------+
				
				
				+-----------------------------------------+
				; Flow Settings                           ;
				+-------------------+---------------------+
				; Option            ; Setting             ;
				+-------------------+---------------------+
				; Start date & time ; 11/13/2008 21:05:31 ;
				; Main task         ; Compilation         ;
				; Revision Name     ; transceiver         ;
				+-------------------+---------------------+
				
				
				+-----------------------------------------------------------------------------------------+
				; Flow Non-Default Global Settings                                                        ;
				+------------------------------------+---------+---------------+-------------+------------+
				; Assignment Name                    ; Value   ; Default Value ; Entity Name ; Section Id ;
				+------------------------------------+---------+---------------+-------------+------------+
				; PARTITION_COLOR                    ; 2147039 ; --            ; --          ; Top        ;
				; PARTITION_NETLIST_TYPE             ; SOURCE  ; --            ; --          ; Top        ;
				; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off     ; --            ; --          ; eda_palace ;
				+------------------------------------+---------+---------------+-------------+------------+
				
				
				+---------------------------------------------------------------+
				; Flow Elapsed Time                                             ;
				+----------------------+--------------+-------------------------+
				; Module Name          ; Elapsed Time ; Average Processors Used ;
				+----------------------+--------------+-------------------------+
				; Analysis & Synthesis ; 00:00:01     ; 1.0                     ;
				; Total                ; 00:00:01     ; --                      ;
				+----------------------+--------------+-------------------------+
				
				
				------------
				; Flow Log ;
				------------
				quartus_map --read_settings_files=on --write_settings_files=off transceiver -c transceiver
				
				
				
							

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