Flow report for top1
Sat Jan 12 17:40:03 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Elapsed Time
5. Flow Log
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; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------+
; Flow Summary ;
+-------------------------+------------------------------------------+
; Flow Status ; Successful - Sat Jan 12 17:40:03 2008 ;
; Quartus II Version ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name ; top1 ;
; Top-level Entity Name ; display ;
; Family ; Cyclone ;
; Device ; EP1C3T144C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 37 / 2,910 ( 1 % ) ;
; Total pins ; 36 / 104 ( 35 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 59,904 ( 0 % ) ;
; Total PLLs ; 0 / 1 ( 0 % ) ;
+-------------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 01/12/2008 17:39:48 ;
; Main task ; Compilation ;
; Revision Name ; top1 ;
+-------------------+---------------------+
+-------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+
; Module Name ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:05 ;
; Fitter ; 00:00:04 ;
; Assembler ; 00:00:02 ;
; Timing Analyzer ; 00:00:01 ;
; Total ; 00:00:12 ;
+----------------------+--------------+
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; Flow Log ;
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quartus_map --read_settings_files=on --write_settings_files=off top1 -c top1
quartus_fit --read_settings_files=off --write_settings_files=off top1 -c top1
quartus_asm --read_settings_files=off --write_settings_files=off top1 -c top1
quartus_tan --read_settings_files=off --write_settings_files=off top1 -c top1 --timing_analysis_only
