Flow report for lcdmpddr
Sat Dec 03 17:54:19 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Elapsed Time
5. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+------------------------------------------+
; Flow Status ; Successful - Sat Dec 03 17:54:15 2005 ;
; Quartus II Version ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name ; lcdmpddr ;
; Top-level Entity Name ; lcdmpddr ;
; Family ; Cyclone ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Production ;
; Total logic elements ; 97 / 12,060 ( < 1 % ) ;
; Total pins ; 45 / 173 ( 26 % ) ;
; Total memory bits ; 0 / 239,616 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-----------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/03/2005 17:53:39 ;
; Main task ; Compilation ;
; Revision Name ; lcdmpddr ;
+-------------------+---------------------+
+-------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+
; Module Name ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:05 ;
; Fitter ; 00:00:10 ;
; Assembler ; 00:00:03 ;
; Timing Analyzer ; 00:00:01 ;
; Total ; 00:00:19 ;
+----------------------+--------------+
------------
; Flow Log ;
------------
quartus_map --import_settings_files=on --export_settings_files=off lcdmpddr -c lcdmpddr
quartus_fit --import_settings_files=off --export_settings_files=off lcdmpddr -c lcdmpddr
quartus_asm --import_settings_files=off --export_settings_files=off lcdmpddr -c lcdmpddr
quartus_tan --import_settings_files=off --export_settings_files=off lcdmpddr -c lcdmpddr --timing_analysis_only
