--------------------------------------------------------------------------------
-- P H I L I P S C O M P A N Y R E S T R I C T E D
--
-- Copyright (c) 1998.
--
-- Philips Electronics N.V.
--
-- Philips Semiconductors
-- Interconnectivity and Processor Peripherals group
-- Bangalore, India
-- All rights reserved. Reproduction in whole or in part is prohibited
-- without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
-- File : usb_new_pvci_cntrl_rtl.vhdl
--
-- Module : PVCI_CONTROLLER
--
-- Project : VPB bus interface to USB1.1 device (USBFS22)
--
-- Author :
--
-- Description : The architecture of PVCI controller block. This module
-- does address decoding.
--
-- Contact address : sanjeev@blr.sc.philips.com
--
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.PCK_GENERAL.all;
library work;
use work.PCK_APB.all;
architecture RTL of PVCI_CNTRL is
signal Error_I: one_bit;
begin
r_data Wr_data
-- Grant generation
gnt
-- Generation of Read and Write signals for the registers in USB slave block
-- by address decoding
Write_Intr_Enable and req = '1') else '0';
Write_Intr_Clear and req = '1') else '0';
Write_Intr_Set and req = '1') else '0';
Write_Cmd_Code and req = '1') else '0';
Write_Transmt_Data and req = '1') else '0';
Write_TxPkt_Lngth and req = '1') else '0';
Write_Usb_Cntrl and req = '1') else '0';
Write_Fiq_Sel and req = '1') else '0';
Read_RxPkt_Lngth and req = '1') else '0';
Read_Intr_Status and req = '1') else '0';
Read_Intr_enable and req = '1') else '0';
Read_Cmd_Data and req = '1') else '0';
Read_Receive_Data and req = '1') else '0';
Read_Usb_Cntrl and req = '1') else '0';
Read_TxPkt_Lngth and req = '1') else '0';
-- Error generation when the address is not correct
Error_I USB_MAX_ADDRESS and req = '1') else '0';
Error
end RTL;
