fifo pointers in verilog gray code utilization for synchronius
资源简介:fifo pointers in verilog gray code utilization for synchronius
上传时间: 2014-11-24
上传用户:silenthink
资源简介:Generic FIFO, writen in verilog hdl
上传时间: 2016-02-18
上传用户:zwei41
资源简介:serial port rs232 in verilog source code
上传时间: 2014-12-03
上传用户:songyue1991
资源简介:it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is requir...
上传时间: 2014-06-26
上传用户:zhuyibin
资源简介:it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
上传时间: 2017-03-22
上传用户:洛木卓
资源简介:it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
上传时间: 2014-01-10
上传用户:kernaling
资源简介:it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.
上传时间: 2017-03-22
上传用户:xymbian
资源简介:it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
上传时间: 2013-12-11
上传用户:yepeng139
资源简介:this is a code for DDS in Verilog
上传时间: 2013-12-03
上传用户:sdq_123
资源简介:code for fpga is written in verilog,cardinality is a thing which is very important
上传时间: 2013-12-20
上传用户:moerwang