您现在的位置是:源码地带 > 资源下载

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

资 源 简 介

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.

相 关 资 源