`timescale 1ns/10ps module myrom_tb; reg read_en_; reg [3:0]addr; wire [3:0]read_data; myrom c1(.read_data(read_data),.addr(addr),.read_en_(read_en_)); initial begin read_en_=1; #5 read_en_=0;
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`define WIDTH 8 module lfsr_updown( clk, //Clock input reset, //Reset input enable, //Enable input up_down, //Up Down input count, //Count output overflow
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//************************************* // file name :five_divider // author :yilong.you // date :October 12,2008 //************************************* module five_divider(
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module fenpin3(clk,reset,clk_out); input clk,reset; output clk_out; reg [1:0]state; reg clk1; assign clk_out=state[0]&clk1; always@(posedge clk or negedge reset) if(!reset) state
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module shift(data_out,data_in,rst_,clk); output[3:0]data_out; input data_in; input rst_; input clk; reg[3:0]data_out; always@(posedge clk or negedge rst_) if(!rst_)
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module sec_counter(clock,reset,load,din,count); input clock,reset,load; input[5:0]din; output [5:0]count; reg [5:0]count; always@(posedge clock or posedge reset)begin
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`timescale 1ns/1ns module adder_tp; reg [3:0] a,b; reg cin; wire [3:0] sum; wire cout; integer i,j; adder4 adder(.sum(sum),.cout(cout),.ina(a),.inb(b),.cin(cin)); always #5 cin=~cin; initial begin
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module TaskWait; //reg NoClock; reg ClockQ; task GenerateWaveform; begin ClockQ=1; #2 ClockQ=0; #2 ClockQ=1; #2 ClockQ=0; end endtask initial GenerateWaveform; end
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module BCDcount60 ( qout , cout , data , load , cin , reset ,
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//*************************************************** // File Name: traffic_light_controller.v // Date: September 29,2008 // author: yilong.you // yilong.you@stu.xjtu.edu.cn //**
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