verilog代码集锦.rar

				module fenpin3(clk,reset,clk_out);				input clk,reset;				output clk_out;								reg [1:0]state;				reg clk1;								assign clk_out=state[0]&clk1;				always@(posedge clk or negedge reset)				   if(!reset)				   	  state				   else				   	 case(state)				   	 	    2'b00:state				   	 	    2'b01:state				   	 	    2'b11:state				   	 	    default:state				   	 endcase				   	 				always@(negedge clk or negedge reset)				   if(!reset)				   	  clk1				   else				   	clk1=state[0]; 				endmodule								`timescale 1ns/1ns				module fenpin3_tb;				reg clk,reset;				wire clk_out;								always #1 clk=~clk;				initial begin					clk=0;					reset=1;					#6 reset=0;					#20 reset=1;					#100$stop;				end  	 				fenpin3 c1(.clk(clk),.reset(reset),.clk_out(clk_out));				endmodule