This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.
The core acts as a slave WISHBONE device.
The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an u ...
This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
jamod is an object oriented implementation of the Modbus protocol, realized 100 in Java. It allows to quickly realize master and slave applications in various transport flavors (IP and serial).
In this work an implementation of a geometric nonlinear controller for chaos synchronization in a Field Programmable Gate Array (FPGA) is presented. The Lorenz chaotic system is used to show the implementation of chaos synchronization via nonlinear controller implemented in a Xilinx FPGA Virtex-II 2 ...
hese are the zip files that are associated with application note
ADSP-BF533 Blackfin Booting Process (EE-240)
example.zip:
Used throughout the EE-note to explain in detail the various booting modes.
BF533 Ez Kit Multiple DXE Boot.zip:
Multi-DXE Boot Example used with the ADSP-BF533 Ez-Kit Lit ...
