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Nios II定制指令用户指南

     Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequen ...

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标签： Nios 定制指令用户

上传时间： 2013-10-12

上传用户：kang1923

ALTERA的FPGA_的AS、PS和Jtag配置模式区别

altera

/dl/39618.html

标签： ALTERA FPGA Jtag 模式

上传时间： 2014-01-02

上传用户：pinksun9

Employing a Single-Chip Transceiver in Femtocell Base-Station Applications

Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective s ...

/dl/39952.html

标签： Base-Station Applications Single-Chip Transceiver

上传时间： 2013-11-05

上传用户：超凡大师

wp379 AXI4即插即用IP

In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting ch ...

/dl/40023.html

标签： AXI4 379 wp 即插即用

上传时间： 2013-11-11

上传用户：csgcd001

XAPP503-针对Xilinx器件的SVF和XSVF文件格式

This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded pro ...

/dl/40051.html

标签： Xilinx XAPP XSVF 503

上传时间： 2015-01-02

上传用户：时代将军

XAPP228 -Virtex器件内的四端口存储器

This application note describes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in ...

/dl/40055.html

标签： Virtex XAPP 228 器件

上传时间： 2014-01-24

上传用户：15527161163

XAPP098 - Spartan FPGA低成本、高效率串行配置

This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration ci ...

/dl/40059.html

标签： Spartan XAPP FPGA 098

上传时间： 2013-11-01

上传用户：wojiaohs

XAPP444 - CPLD配件,技巧和窍门

Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determ ...

/dl/40063.html

标签： XAPP CPLD 444 配件

上传时间： 2014-01-11

上传用户：a471778

XAPP440 - Xilinx CPLD的上电性能

Applying power to a standard logic chip, SRAM, or EPROM, usually results in output pinstracking the applied voltage as it rises. Programmable logic attempts to emulate that behavior,but physics forbids perfect emulation, due to the device programmability. It requires care tospecify the pin behavio ...

/dl/40065.html

标签： Xilinx XAPP CPLD 440

上传时间： 2013-11-24

上传用户：253189838

XAPP144 -设计CPLD多电压系统

Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for han ...

/dl/40067.html

标签： XAPP CPLD 144 电压

上传时间： 2013-11-10

上传用户：yy_cn

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As 2153条

按分类查找:

Nios II定制指令用户指南

ALTERA的FPGA_的AS、PS和Jtag配置模式区别

Employing a Single-Chip Transceiver in Femtocell Base-Station Applications

wp379 AXI4即插即用IP

XAPP503-针对Xilinx器件的SVF和XSVF文件格式

XAPP228 -Virtex器件内的四端口存储器

XAPP098 - Spartan FPGA低成本、高效率串行配置

XAPP444 - CPLD配件,技巧和窍门

XAPP440 - Xilinx CPLD的上电性能

XAPP144 -设计CPLD多电压系统

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