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XAPP143-利用Verilog来创建CPLD设计

This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state m ...

/dl/40069.html

标签： Verilog XAPP CPLD 143

上传时间： 2013-11-11

上传用户：y13567890

XAPP105 - CPLD VHDL介绍

This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPLDs). Specifically included are those design practices that translate soundlyto CPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLD ...

/dl/40070.html

标签： XAPP CPLD VHDL 105

上传时间： 2013-11-21

上传用户：gtf1207

WP247 - Virtex-5系列高级封装

The exacting technological demands created byincreasing bandwidth requirements have given riseto significant advances in FPGA technology thatenable engineers to successfully incorporate highspeedI/O interfaces in their designs. One aspect ofdesign that plays an increasingly important role isthat o ...

/dl/40072.html

标签： Virtex 247 WP 高级封装

上传时间： 2013-11-07

上传用户：wanghui2438

XAPP944 - 将Xilinx CoolRunner-II CPLD用作数据流开关

  This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” se ...

/dl/40092.html

标签： CoolRunner-II Xilinx XAPP CPLD

上传时间： 2013-12-16

上传用户：qwer0574

XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥

  The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Spec ...

/dl/40099.html

标签： PCI-X XAPP DIMM 708

上传时间： 2013-11-24

上传用户：18707733937

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接  The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and ...

/dl/40104.html

标签： XAPP FPGA Bank 520

上传时间： 2013-11-06

上传用户：wentianyou

US Navy VHDL Modelling Guide

  This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the deve ...

/dl/40131.html

标签： Modelling Guide Navy VHDL

上传时间： 2013-11-20

上传用户：pzw421125

VHDL,Verilog,System verilog比较

  本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers ...

/dl/40147.html

标签： Verilog verilog System VHDL

上传时间： 2014-03-03

上传用户：zhtzht

CPLD和FPGA设计介绍

Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system ...

/dl/40148.html

标签： CPLD FPGA

上传时间： 2013-10-22

上传用户：lmq0059

allegro cx manual教程

We would like to welcome you as a user of the Allegro CX, a rugged, handheld ﬁ  eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegr ...

/dl/40217.html

标签： allegro manual cx 教程

上传时间： 2015-01-02

上传用户：zhangyi99104144

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As 2153条

按分类查找:

XAPP143-利用Verilog来创建CPLD设计

XAPP105 - CPLD VHDL介绍

WP247 - Virtex-5系列高级封装

XAPP944 - 将Xilinx CoolRunner-II CPLD用作数据流开关

XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

US Navy VHDL Modelling Guide

VHDL,Verilog,System verilog比较

CPLD和FPGA设计介绍

allegro cx manual教程

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