control.c.svn-base

#include "reg51.h" #include "../include/c51.h" #include "../include/control.h" uchar CursorEnable;//bit 0 enable bit uchar Cursor_x; uchar Cursor_y; uchar IsDoInit; uchar IsNeedBee

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control.1

V 50 K 335337310500 control Y 1 D 0 0 220 140 Z 10 i 9 P 1 0 100 20 100 0 2 0 L 20 100 10 0 2 0 1 0 CLK48M A 0 110 10 0 2 0 PINTYPE=IN P 2 0 80 20 80 0 2 0 L 20 80 10 0 2 0 1 0 rst A 0 90 1

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control.hpj

http://www.codebf.com/read/299888/3849699

control.plg

@P: Worst Slack : 1.920 @P: control|CLK48M - Estimated Frequency : 133.0 MHz @P: control|CLK48M - Requested Frequency : 100.0 MHz @P: control|CLK48M - Estimated Period : 7.521 @P: control|CLK

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control.tlg

Selecting top level module control @N: CG364 :"C:\Actelprj\PWM\hdl\PWM_contr.v":2:7:2:13|Synthesizing module control

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control.areasrr

---------------------------------------------------------------------- Report for cell control.verilog Cell usage: cell

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control.srd

f "noname"; #file 0 f "d:\libero\synplify\synplify_862h\lib\proasic\fusion.v"; #file 1 f "c:\actelprj\pwm\hdl\pwm_contr.v"; #file 2 VNAME 'work.control.verilog'; # view id 0 @EuyRsFCDN88CRsbN0HRDL

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control.sdf

(DELAYFILE (SDFVERSION "OVI 2.1") (DESIGN "control") (DATE "123") (VENDOR "ProASIC3") (PROGRAM "Synplify") (VERSION "9.0.0, Build 368R") (DIVIDER /) (VOLTAGE 2.500000:2.500000:2.500000) (PROC

http://www.codebf.com/read/299888/3849726

control.edn

(edif control (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2007 9 25 8 33 12) (author "Synplicity, Inc.") (program

http://www.codebf.com/read/299888/3849728

control.tcl

# Created by Libero Project Manager 8.0.1.13 # Tue Sep 25 08:35:28 2007 # (NEW DESIGN) # create a new design new_design -name "control" -family "Fusion" set_device -die "AFS600" -package "256

http://www.codebf.com/read/299888/3849739