Core_PWM,verilog语言编写
源代码在线查看： control.areasrr
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Report for cell control.verilog
Cell usage:
cell count area count*area
DFN1C1 99 1.0 99.0
MX2 56 1.0 56.0
XNOR3 56 1.0 56.0
AND3 32 1.0 32.0
AO13 32 1.0 32.0
XOR2 26 1.0 26.0
AO1D 17 1.0 17.0
ZOR3 16 1.0 16.0
AO1B 16 1.0 16.0
DFN1P1 15 1.0 15.0
OUTBUF 14 0.0 0.0
OR3A 8 1.0 8.0
AX1B 8 1.0 8.0
AND2 8 1.0 8.0
OR3B 8 1.0 8.0
NOR3A 8 1.0 8.0
NOR2B 5 1.0 5.0
INBUF 4 0.0 0.0
NOR3C 4 1.0 4.0
BUFF 2 1.0 2.0
OR2A 2 1.0 2.0
CLKBUF 1 0.0 0.0
CLKINT 1 0.0 0.0
OR2 1 1.0 1.0
OR2B 1 1.0 1.0
INV 1 1.0 1.0
OAI1 1 1.0 1.0
VCC 1 0.0 0.0
GND 1 0.0 0.0
TOTAL 444 422.0
