Core_PWM,verilog语言编写

				V 50
				K 335337310500 control
				Y 1
				D 0 0 220 140
				Z 10
				i 9
				P 1 0 100 20 100 0 2 0
				L 20 100 10 0 2 0 1 0 CLK48M
				A 0 110 10 0 2 0 PINTYPE=IN
				P 2 0 80 20 80 0 2 0
				L 20 80 10 0 2 0 1 0 rst
				A 0 90 10 0 2 0 PINTYPE=IN
				P 3 220 100 200 100 0 3 0
				L 110 100 10 0 2 0 1 0 addr[2:0]
				A 200 110 10 0 2 0 PINTYPE=OUT
				P 4 220 80 200 80 0 3 0
				L 110 80 10 0 2 0 1 0 data[7:0]
				A 200 90 10 0 2 0 PINTYPE=OUT
				P 5 220 60 200 60 0 3 0
				L 180 60 10 0 2 0 1 0 CS
				A 200 70 10 0 2 0 PINTYPE=OUT
				P 6 220 40 200 40 0 3 0
				L 180 40 10 0 2 0 1 0 WE
				A 200 50 10 0 2 0 PINTYPE=OUT
				U 20 10 10 0 2 3 DEVICE=control
				U 20 0 10 0 3 0 VFILE=E:/1/2/PWM/Project/PWM/hdl/PWM_contr.v
				U 20 -10 10 0 3 0 ACCEL=VCS
				U 20 -20 10 0 3 0 LEVEL=VERILOG
				U 20 -30 10 0 3 0 VERILOG=control
				U 20 -40 10 0 3 0 PINORDER=CLK48M rst addr[2:0] data[7:0] CS WE 
				b 20 20 200 120
				E