Assembler report for Div20PLL
Tue Feb 27 10:45:52 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.sof
6. Assembler Device Options: D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.pof
7. Assembler Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Feb 27 10:45:52 2007 ;
; Revision Name ; Div20PLL ;
; Top-level Entity Name ; Div20PLL ;
; Family ; Stratix ;
; Device ; EP1S10F484C5 ;
+-----------------------+---------------------------------------+
+-----------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+--------------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; JTAG user code for target device ; Ffffffff ; Ffffffff ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; JTAG user code for configuration device ; Ffffffff ; Ffffffff ;
; Configuration device auto user code ; Off ; Off ;
; Auto-increment JTAG user code for multiple configuration devices ; On ; On ;
; Disable CONF_DONE and nSTATUS pull-ups on configuration device ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
+--------------------------------------------------------------------------------+----------+---------------+
+-------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------+
; File Name ;
+-------------------------------------------------+
; D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.sof ;
; D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.pof ;
+-------------------------------------------------+
+---------------------------------------------------------------------------+
; Assembler Device Options: D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.sof ;
+----------------+----------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------+
; Device ; EP1S10F484C5 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x001344E3 ;
+----------------+----------------------------------------------------------+
+---------------------------------------------------------------------------+
; Assembler Device Options: D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.pof ;
+----------------+----------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------+
; Device ; EPC4 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x06323591 ;
+----------------+----------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Feb 27 10:45:49 2007
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Div20PLL -c Div20PLL
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Feb 27 10:45:52 2007
Info: Elapsed time: 00:00:04
