Verilog编写的UART程序源代码。测试成功。支持字符串发送

源代码在线查看: uart.tan.summary

软件大小: 1513 K
上传用户: happy_christina
关键词: Verilog UART 编写 程序
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相关代码

				--------------------------------------------------------------------------------------
				Timing Analyzer Summary
				--------------------------------------------------------------------------------------
				
				Type           : Worst-case tsu
				Slack          : N/A
				Required Time  : None
				Actual Time    : 5.849 ns
				From           : rs232_rx
				To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0]
				From Clock     : --
				To Clock       : clk
				Failed Paths   : 0
				
				Type           : Worst-case tco
				Slack          : N/A
				Required Time  : None
				Actual Time    : 8.657 ns
				From           : my_uart_tx:my_uart_tx|rs232_tx_r
				To             : rs232_tx
				From Clock     : clk
				To Clock       : --
				Failed Paths   : 0
				
				Type           : Worst-case tpd
				Slack          : N/A
				Required Time  : None
				Actual Time    : 9.426 ns
				From           : rs232_rx
				To             : altera_auto_signaltap_0_rs232_rx_ae
				From Clock     : --
				To Clock       : --
				Failed Paths   : 0
				
				Type           : Worst-case th
				Slack          : N/A
				Required Time  : None
				Actual Time    : 2.009 ns
				From           : altera_internal_jtag~TDIUTAP
				To             : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
				From Clock     : --
				To Clock       : altera_internal_jtag~TCKUTAP
				Failed Paths   : 0
				
				Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
				Slack          : N/A
				Required Time  : None
				Actual Time    : 95.91 MHz ( period = 10.426 ns )
				From           : sld_hub:sld_hub_inst|jtag_debug_mode
				To             : sld_hub:sld_hub_inst|hub_tdo_reg
				From Clock     : altera_internal_jtag~TCKUTAP
				To Clock       : altera_internal_jtag~TCKUTAP
				Failed Paths   : 0
				
				Type           : Clock Setup: 'clk'
				Slack          : N/A
				Required Time  : None
				Actual Time    : 156.01 MHz ( period = 6.410 ns )
				From           : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0]
				To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[4]
				From Clock     : clk
				To Clock       : clk
				Failed Paths   : 0
				
				Type           : Total number of failed paths
				Slack          : 
				Required Time  : 
				Actual Time    : 
				From           : 
				To             : 
				From Clock     : 
				To Clock       : 
				Failed Paths   : 0
				
				--------------------------------------------------------------------------------------
				
							

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