--------------------------------------------------------------------------------
--
-- P H I L I P S C O M P A N Y R E S T R I C T E D
--
-- Copyright (c) 1998.
--
-- Philips Electronics N.V.
--
-- Philips Semiconductors
-- Interconnectivity and Processor Peripheral group
-- Bangalore,India
-- All rights reserved. Reproduction in whole or in part is prohibited
-- without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
-- File : usb_new_glue_rtl.vhdl
--
-- Module : GLUE
--
-- Project : VPB bus Interface to USB 1.1 Device(USBFS22)
--
-- Author :
--
-- Description :The architecture of GLUE module. This module does the
-- conversion of unsigned to std_logic & vice versa.
--
-- Status :
--
-- Contact address :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.PCK_GENERAL.all;
use work.PCK_USB.all;
use work.PCK_CONFIGURATION.all;
use work.PCK_SETUP.all;
library work;
use work.PCK_APB.all;
architecture RTL of GLUE is
begin
-- pvci interface signals
r_data gnt USB_clk USB_reset_n pvci_reset_n_out USB_req USB_address USB_rnw USB_w_data USB_Int_Req_Irq USB_Int_Req_Fiq
---------- Clocks ---------
Clk12MHzRef Clk48MHz USB_NeedClk
FsClk HB_UsbLineBits(0) HB_UsbLineBits(1) HB_UsbDifBit
HC_ResetDevice FALSE);
USB_BitClk_Out
---------- Connect ---------
USB_Connect_N
---------- Misc ---------
ChipID PINConfigArray FALSE); ---- ????
Suspend_In TestMode VBusAvailable
---------- Raminterface ---------
RxRAM_DQ_In TxRAM_DQ_In
USB_RxRAM_E_N USB_RxRAM_W_N USB_RxRAM_G_N USB_RxRAM_A USB_RxRAM_DQ_Out
USB_TxRAM_E_N USB_TxRAM_W_N USB_TxRAM_G_N USB_TxRAM_A USB_TxRAM_DQ_Out
---------- Suspend ---------
USB_Suspend
---------- General ---------
RemoteWakeup
---------- Upstream port ---------
UP_DsLineBits(0) UP_DsLineBits(1) USB_UP_LED_N USB_UP_TxDM USB_UP_TxDP USB_UP_TxEnable_N
end RTL;
