--------------------------------------------------------------------------------
--
-- P H I L I P S C O M P A N Y R E S T R I C T E D
--
-- Copyright (c) 1998.
--
-- Philips Electronics N.V.
--
-- Philips Semiconductors
-- Interconnectivity and Processor Peripheral group
-- Bangalore,India
-- All rights reserved. Reproduction in whole or in part is prohibited
-- without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
-- File : usb_new_usbpvci_ent.vhdl
--
-- Module : USBPVCI
--
-- Project : VPB bus Interface to USB 1.1 Device(USBFS22)
--
-- Author :
--
-- Description : The entity of USBPVCI block
--
-- Status :
--
-- Contact address :
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.PCK_GENERAL.all;
use work.PCK_CONFIGURATION.all;
use work.PCK_SETUP.all;
use work.PCK_HANDLERS.all;
use work.PCK_USB.all;
library work;
use work.PCK_APB.all;
entity USBPVCI is
port(
-- USB Clocks
USB_BitClk: in std_logic; -- Recovered bit clock 12 Mhz
USB_BitClk_Out: out std_logic; -- Recovered bit clock 12 Mhz
USB_MainClk: in std_logic; -- Main clock 48 Mhz
USB_NeedClk: out std_logic; -- USB Core needs clock
-- Connect
USB_Connect_N: out std_logic; -- Controls switch for softconnect
USB_VBus: in std_logic; -- Bus power is present
-- Test signal
USB_TestMode: in std_logic; -- Select test mode
-- USB asynchronous reset
USB_AsynReset_N: in std_logic;
-- Interface to SRAM
USB_RxRAM_E_N: out std_logic; -- RAM chip enable
USB_RxRAM_W_N: out std_logic; -- RAM write enable
USB_RxRAM_G_N: out std_logic; -- RAM read enable
USB_RxRAM_A: out std_logic_vector(RxRAMAddr_Width-1 downto 0); -- RAM address
USB_RxRAM_DQ_In: in std_logic_vector(31 downto 0); -- RAM data out bus
USB_RxRAM_DQ_Out: out std_logic_vector(31 downto 0); -- RAM data in bus
USB_TxRAM_E_N: out std_logic; -- RAM chip enable
USB_TxRAM_W_N: out std_logic; -- RAM write enable
USB_TxRAM_G_N: out std_logic; -- RAM read enable
USB_TxRAM_A: out std_logic_vector(TxRAMAddr_Width-1 downto 0); -- RAM address
USB_TxRAM_DQ_In: in std_logic_vector(31 downto 0); -- RAM data out bus
USB_TxRAM_DQ_Out: out std_logic_vector(31 downto 0); -- RAM data in bus
-- Suspend
USB_Suspend: out std_logic; -- Suspend
-- Interface to APB WRAPPER
r_data: out std_logic_vector(31 downto 0); -- Read data
gnt: out std_logic; -- Grant
clk: in std_logic; -- Clock
pvci_reset_n: in std_logic; -- Reset
req: in std_logic; -- Request
address: in std_logic_vector(7 downto 0); -- Address
rnw: in std_logic; -- Read or Write
w_data: in std_logic_vector(31 downto 0); -- Write data
error: out std_logic; -- error
-- Interrupt request lines
USB_Int_Req_Irq: out std_logic; -- Irq interrupt to the system
USB_Int_Req_Fiq: out std_logic; -- Fiq interrupt to the system
USB_UP_LED_N: out std_logic; -- LED
USB_UP_RxDM: in std_logic; -- Rx D-
USB_UP_RxDP: in std_logic; -- Rx D+
USB_UP_RxRCV: in std_logic; -- Rx RCV
USB_UP_TxDM: out std_logic; -- Tx D-
USB_UP_TxDP: out std_logic; -- Tx D+
USB_UP_TxEnable_N: out std_logic -- Tx Enable
);
end USBPVCI;
