// ?????
//------------------------------------------------------------------------------------------------------------
module clk_gen (clk,reset,clk1,clk2,clk4,fetch,alu_clk);
input clk,reset;
output clk1,clk2,clk4,fetch,alu_clk;
wire clk,reset;
reg clk2,clk4,fetch,alu_clk;
reg[7:0] state;
parameter S1 = 8'b00000001,
S2 = 8'b00000010,
S3 = 8'b00000100,
S4 = 8'b00001000,
S5 = 8'b00010000,
S6 = 8'b00100000,
S7 = 8'b01000000,
S8 = 8'b10000000,
idle = 8'b00000000;
assign clk1 = ~clk;
always @(negedge clk)
if(reset)
begin
clk2 clk4 fetch alu_clk state end
else
begin
case(state)
S1:
begin
clk2 alu_clk state end
S2:
begin
clk2 clk4 alu_clk state end
S3:
begin
clk2 state end
S4:
begin
clk2 clk4 fetch state end
S5:
begin
clk2 state end
S6:
begin
clk2 clk4 state end
S7:
begin
clk2 state end
S8:
begin
clk2 clk4 fetch state end
idle: state default: state endcase
end
endmodule
//--------------------------------------------------------------------------------
