异步FIFO模块： module asynfifo(rst,iclk,oclk,din,wren,rden,dout,full,empty) 异步FIFO的tenchbench： module

				module asynfifo(rst,iclk,oclk,din,wren,rden,dout,full,empty);
				input 	rst;
				input 	iclk;
				input 	oclk;
				input 	[7:0] din;
				input 	wren;
				input 	rden;
				output  [7:0] dout;
				output 	full;
				output 	empty;
				reg 	[7:0] dout;
				reg 	full;
				reg 	empty;
				reg 	[9:0] wp_bin;
				reg 	[9:0] wp_bin_next;
				reg 	[9:0] wp_gray;
				wire 	[9:0] wp_gray_next;
				reg 	[9:0] rp_bin;
				reg 	[9:0] rp_bin_next;
				reg 	[9:0] rp_gray;
				wire 	[9:0] rp_gray_next;
				reg 	[7:0] rams[0:1023];
				always @(posedge iclk or posedge rst)
				begin
					if(rst)	wp_bin 					else 	wp_bin 				end
				always @(wp_bin or wren or full)
				begin
					if(wren&&!full)
					  	wp_bin_next = wp_bin + 1'b1;
					else 	wp_bin_next = wp_bin;
				end
				assign wp_gray_next = wp_bin_next^{wp_bin_next>>1};
				always @(posedge iclk or posedge rst)
				begin
					if(rst) wp_gray 					else 	wp_gray 				end
				always @(posedge oclk or posedge rst)
				begin
					if(rst) rp_bin 					else 	rp_bin 				end
				always @(rp_bin or rden or empty)
				begin
					if(rden&&!empty)
					  	rp_bin_next = rp_bin + 1'b1;
					else 	rp_bin_next = rp_bin;
				end
				assign rp_gray_next = rp_bin_next^{rp_bin_next>>1};
				always @(posedge oclk or posedge rst)
				begin
					if(rst) rp_gray 					else 	rp_gray 				end
				always @(posedge iclk)
				begin
					if(wren&&!full)  rams[wp_gray] 				end
				always @(posedge oclk)
				begin
					if(rden&&!empty) dout 				end
				always @(posedge iclk or posedge rst)
				begin
					if(rst) full 					else 
						if(wp_gray_next==rp_gray&&wren) full 						else 	full 				end
				always @(posedge oclk or posedge rst)
				begin
					if(rst) empty 					else 
						if(rp_gray_next==wp_gray&&rden) empty 						else 	empty 				end
				endmodule