异步FIFO模块： module asynfifo(rst,iclk,oclk,din,wren,rden,dout,full,empty) 异步FIFO的tenchbench： module

				`timescale 1ns/1ns				`include  "asynfifo.v"				module   tb_asynfifo;				 reg         rst;				 reg         iclk;				 reg         oclk;				 reg  [7:0]  din;				 wire [7:0]  dout;				 wire        full;				 wire        empty; 				 wire        wren;				 wire        rden;				 integer     fh;				 integer     wh;				 //initiation				 asynfifo T_asynfifo(				           .rst(rst),				           .iclk(iclk),				           .oclk(oclk),				           .din (din) ,				           .wren(wren),				           .rden(rden),				           .dout(dout),				           .full(full),				           .empty(empty)				                    );				 //enable				 assign      wren = 1;				 assign      rden = 1;								 //rst				 initial				 begin				   rst = 1;				   #50 rst = 0;				 end				 				 //iclk				 initial    iclk = 0;				 always     #5  iclk = ~iclk;				 				 //oclk				 initial    oclk = 0;				 always     #10  oclk = ~oclk;				 				 //file initiation				 initial    fh=$fopen("asynfifo.v","r");				 initial    wh=$fopen("des.bak","w");				 //din				 always @(negedge iclk)				 begin				      wait (rst==0);				      if (wren&&!full)				         din = $fgetc(fh);				 end				 //dout				 always @(negedge oclk)				 begin 				       wait(rst==0);				       if (dout==8'hFF)				       begin				         $fclose(fh);				         $fclose(wh);				         $finish;				       end				       if (rden&&!empty)				         $fwrite(wh,"%c",dout);				 end				endmodule