--------------------------------------------------------------------------------
--
-- P H I L I P S C O M P A N Y R E S T R I C T E D
--
-- Copyright (c) 1998.
--
-- Philips Electronics N.V.
--
-- Philips Semiconductors
-- Interconnectivity and Processor Peripheral group
-- Bangalore,India
-- All rights reserved. Reproduction in whole or in part is prohibited
-- without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
-- File : usb_new_pvci_eng_ent.vhdl
--
-- Module : PVCI_ENG_ENT
--
-- Project : VPB bus Interface to USB 1.1 Device(USBFS22)
--
-- Author :
--
-- Description : The ent of PVCI_ENG block
--
-- Status :
--
-- Contact address :
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.PCK_GENERAL.all;
use work.PCK_HANDLERS.all;
use work.PCK_CONFIGURATION.all;
library work;
use work.PCK_APB.all;
entity PVCI_ENG is
port(
-- Interface to EP_HANDLER modlue
Trans_Enable: in one_bit; -- Data transfer enable
Read: in one_bit; -- '1' read data
EP_number: in Int_EndPointType; -- Physical endpoint number
Data_Out: in byte; -- Data bus for OUT endpoints
End_Transfer: in one_bit; -- End of transfer for packet data
EndTransfer_Cmd: in one_bit; -- End of transfer for command data
USBEp0Intr_Set: in one_bit; -- USB Ep0 interrupt
USBEp1Intr_Set: in one_bit; -- USB Ep1 interrupt
USBEp2Intr_Set: in one_bit; -- USB Ep2 interrupt
USBEp3Intr_Set: in one_bit; -- USB Ep3 interrupt
USBEp4Intr_Set: in one_bit; -- USB Ep4 interrupt
USBEp5Intr_Set: in one_bit; -- USB Ep5 interrupt
USBEp6Intr_Set: in one_bit; -- USB Ep6 interrupt
USBEp7Intr_Set: in one_bit; -- USB Ep7 interrupt
USBDevIntr_Set: in one_bit; -- USB Dev interrupt
USBToggleBuffer: in T_ToggleArray; -- USB buffer toggle
UCToggleBuffer: in T_ToggleArray; -- UC buffer toggle
FullBuffer_UC: in T_Full; -- Buffer full for endpoints
PI_IsoToggle: in integer range 0 to 1; -- ISO buffer toggle
RxError: in boolean; -- Error in packet transfer
reg_ram_read: in one_bit; -- Start of IN transfer
reg_ram_tag: in Int_EndPointType; -- Physical endpoint number
CommandData: in byte; -- Command data
CmdDataValid: in boolean; -- Command data valid
CmdAccept: in boolean; -- Handshake signal for Command accepted
CommandCodeChannel: out eleven_bits; -- Command code
CmdCodeValid_Out: out boolean; -- Command code valid
If_Busy: out boolean; -- Interface busy
Read_Req: out one_bit; -- ????
Data_In: out byte; -- Data bus for IN data
TxDest_NData: out nine_bits; -- Number of bytes for IN packet
Rx_N_data: in integer range 0 to MAX_OVERFLOW_SIZE; -- Packet size
-- Interface to RAM module
RxRAM_DQ_In: in four_bytes; -- RAM data in-bus (32-bits)
RxRAM_E_N: out one_bit; -- RAM enable, active low
RxRAM_W_N: out one_bit; -- RAM write, active low
RxRAM_G_N: out one_bit; -- RAM grant(read), active low
RxRAM_A: out RxRAMAddr_bits; -- RAM address bus (??-bits)
RxRAM_DQ_Out: out four_bytes; -- RAM data out-bus(32-bits)
-- Interface to TRNSMT_RAM module
TxRAM_E_N: out one_bit; -- RAM enable, active low
TxRAM_W_N: out one_bit; -- RAM write, active low
TxRAM_G_N: out one_bit; -- RAM grant(read), active low
TxRAM_A: out TxRAMAddr_bits; -- RAM address bus
TxRAM_DQ_In: in four_bytes; -- RAM data in-bus
TxRAM_DQ_Out: out four_bytes; -- RAM data out-bus
-- Interrupt signals
Intr_Request_Irq: out one_bit; -- Irq Interrupt request to processor
Intr_Request_Fiq: out one_bit; -- Fiq Interrupt request to processor
-- Interface to APB_WRAPPER module
clk: in one_bit; -- PVCI clock
pvci_reset_n: in one_bit; -- Reset
req: in one_bit; -- Request
address: in byte; -- Address
rnw: in one_bit; -- '0' write, '1' read
w_data: in four_bytes; -- Write data
gnt: out one_bit; -- Grant
r_data: out four_bytes; -- Read data
error: out one_bit -- Error
);
end PVCI_ENG;
