-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
-- Shift direction: right/left (right active high)
--
-- CLK active : high
-- CLR active : high
-- CLR type : synchronous
-- SET active : high
-- SET type : synchronous
-- LOAD active : high
-- CE active : high
-- SERIAL input : SI ...
MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 Shift Registers
Description: Demonstrate USART0 in two-way SPI mode. Data are read from
an HC165, and same data written back to the HC164.
ACLK = n/a MCLK = SMCLK = default DCO = UCLK0 = DCO/2
* USART0 control bits are in different SFR s from ...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift ...
This m file simulates a differential phase shift keyed (DPSK) ultra wide bandwidth(UWB) system using a fifth derivative waveform equation of a Gaussian pulse.
