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XAPP452-Spartan-3高级配置架构

This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide th ...

/dl/32580.html

标签： Spartan XAPP 452 架构

上传时间： 2013-11-05

上传用户：透明的心情

Virtex-6 FPGA PCB设计手册

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in ...

/dl/32592.html

标签： Virtex FPGA PCB 设计手册

上传时间： 2014-01-13

上传用户：竺羽翎2222

WP200-将Spartan-3 FPGA用作远程数码相机的低成本控制器

  The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for ...

/dl/32597.html

标签： Spartan FPGA 200 WP

上传时间： 2013-12-10

上传用户：zgu489

XAPP806 -决定DDR反馈时钟的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microproces ...

/dl/32600.html

标签： XAPP 806 DDR DCM

上传时间： 2013-10-15

上传用户：euroford

XAPP719 -利用USR_ACCESS寄存器实现PowerPC高速缓存配置

The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving ...

/dl/32602.html

标签： USR_ACCESS PowerPC XAPP 719

上传时间： 2013-11-13

上传用户：我累个乖乖

XAPP740利用AXI互联设计高性能视频系统

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizat ...

/dl/32619.html

标签： XAPP 740 AXI 互联

上传时间： 2013-11-14

上传用户：fdmpy

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接  The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and ...

/dl/32622.html

标签： XAPP FPGA Bank 520

上传时间： 2013-11-19

上传用户：yyyyyyyyyy

通信的数学理论

The fundamental problem of communication is that of reproducing at one point either exactly or approximately a message selected at another point. Frequently the messages have meaning; that is they refer to or are correlated according to some system with certain physical or conceptual entities.

/dl/32624.html

标签： 通信

上传时间： 2013-10-31

上传用户：liuxinyu2016

CPLD库指南

Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the D ...

/dl/32639.html

标签： CPLD

上传时间： 2013-10-22

上传用户：李哈哈哈

Virtex-5 GTP Transceiver Wizar

The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standa ...

/dl/32709.html

标签： Transceiver Virtex Wizar GTP

上传时间： 2013-10-23

上传用户：leyesome

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Or 1698条

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XAPP452-Spartan-3高级配置架构

Virtex-6 FPGA PCB设计手册

WP200-将Spartan-3 FPGA用作远程数码相机的低成本控制器

XAPP806 -决定DDR反馈时钟的最佳DCM相移

XAPP719 -利用USR_ACCESS寄存器实现PowerPC高速缓存配置

XAPP740利用AXI互联设计高性能视频系统

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

通信的数学理论

CPLD库指南

Virtex-5 GTP Transceiver Wizar

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