Assembler report for ADC_SEG8_DISPLAY
Wed Apr 14 19:34:38 2010
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Apr 14 19:34:38 2010 ;
; Revision Name ; ADC_SEG8_DISPLAY ;
; Top-level Entity Name ; ADC_SEG8_DISPLAY ;
; Family ; MAX7000S ;
; Device ; EPM7128SQC100-15 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; JTAG user code for target device ; Ffff ; Ffff ;
; Auto user code ; Off ; Off ;
; Security bit ; Off ; Off ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Use smart compilation ; Off ; Off ;
+-----------------------------------------------------------------------------+----------+---------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Wed Apr 14 19:34:38 2010
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ADC_SEG8_DISPLAY -c ADC_SEG8_DISPLAY
Warning: Can't generate programming files because you are currently using the Quartus II software in Evaluation Mode
Info: Quartus II Assembler was successful. 0 errors, 1 warning
Info: Allocated 115 megabytes of memory during processing
Info: Processing ended: Wed Apr 14 19:34:39 2010
Info: Elapsed time: 00:00:01
