VHDLADC数码管动态扫描.rar

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相关代码

				EDA Netlist Writer report for ADC_SEG8_DISPLAY
				Wed Apr 14 19:34:43 2010
				Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
				
				
				---------------------
				; Table of Contents ;
				---------------------
				  1. Legal Notice
				  2. EDA Netlist Writer Summary
				  3. Simulation Settings
				  4. Simulation Generated Files
				  5. Timing Analysis Settings
				  6. Timing Analysis Generated Files
				  7. EDA Netlist Writer Messages
				
				
				
				----------------
				; Legal Notice ;
				----------------
				Copyright (C) 1991-2007 Altera Corporation
				Your use of Altera Corporation's design tools, logic functions 
				and other software and tools, and its AMPP partner logic 
				functions, and any output files from any of the foregoing 
				(including device programming or simulation files), and any 
				associated documentation or information are expressly subject 
				to the terms and conditions of the Altera Program License 
				Subscription Agreement, Altera MegaCore Function License 
				Agreement, or other applicable license agreement, including, 
				without limitation, that your use is for the sole purpose of 
				programming logic devices manufactured by Altera and sold by 
				Altera or its authorized distributors.  Please refer to the 
				applicable agreement for further details.
				
				
				
				+------------------------------------------------------------------------+
				; EDA Netlist Writer Summary                                             ;
				+--------------------------------+---------------------------------------+
				; EDA Netlist Writer Status      ; Successful - Wed Apr 14 19:34:43 2010 ;
				; Revision Name                  ; ADC_SEG8_DISPLAY                      ;
				; Top-level Entity Name          ; ADC_SEG8_DISPLAY                      ;
				; Family                         ; MAX7000S                              ;
				; Simulation Files Creation      ; Successful                            ;
				; Timing Analysis Files Creation ; Successful                            ;
				+--------------------------------+---------------------------------------+
				
				
				+--------------------------------------------------------------------------------------------------------------+
				; Simulation Settings                                                                                          ;
				+--------------------------------------------------------------------------------------------+-----------------+
				; Option                                                                                     ; Setting         ;
				+--------------------------------------------------------------------------------------------+-----------------+
				; Tool Name                                                                                  ; ModelSim (VHDL) ;
				; Generate netlist for functional simulation only                                            ; Off             ;
				; Time scale                                                                                 ; 1 ps            ;
				; Truncate long hierarchy paths                                                              ; Off             ;
				; Map illegal HDL characters                                                                 ; Off             ;
				; Flatten buses into individual nodes                                                        ; Off             ;
				; Maintain hierarchy                                                                         ; Off             ;
				; Bring out device-wide set/reset signals as ports                                           ; Off             ;
				; Enable glitch filtering                                                                    ; Off             ;
				; Do not write top level VHDL entity                                                         ; Off             ;
				; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off             ;
				; Architecture name in VHDL output netlist                                                   ; structure       ;
				+--------------------------------------------------------------------------------------------+-----------------+
				
				
				+----------------------------------------------------------------------------+
				; Simulation Generated Files                                                 ;
				+----------------------------------------------------------------------------+
				; Generated Files                                                            ;
				+----------------------------------------------------------------------------+
				; E:/毕设/软件/ADC_SEG8_DISPLAY/simulation/modelsim/ADC_SEG8_DISPLAY.vho     ;
				; E:/毕设/软件/ADC_SEG8_DISPLAY/simulation/modelsim/ADC_SEG8_DISPLAY_vhd.sdo ;
				+----------------------------------------------------------------------------+
				
				
				+--------------------------------------------------------+
				; Timing Analysis Settings                               ;
				+-------------------------------------+------------------+
				; Option                              ; Setting          ;
				+-------------------------------------+------------------+
				; Tool Name                           ; PrimeTime (VHDL) ;
				; Time scale                          ; 1 ps             ;
				; Truncate long hierarchy paths       ; Off              ;
				; Map illegal HDL characters          ; Off              ;
				; Flatten buses into individual nodes ; Off              ;
				+-------------------------------------+------------------+
				
				
				+----------------------------------------------------------------------------+
				; Timing Analysis Generated Files                                            ;
				+----------------------------------------------------------------------------+
				; Generated Files                                                            ;
				+----------------------------------------------------------------------------+
				; E:/毕设/软件/ADC_SEG8_DISPLAY/timing/primetime/ADC_SEG8_DISPLAY.vho        ;
				; E:/毕设/软件/ADC_SEG8_DISPLAY/timing/primetime/ADC_SEG8_DISPLAY_vhd.sdo    ;
				; E:/毕设/软件/ADC_SEG8_DISPLAY/timing/primetime/ADC_SEG8_DISPLAY_pt_vhd.tcl ;
				+----------------------------------------------------------------------------+
				
				
				+-----------------------------+
				; EDA Netlist Writer Messages ;
				+-----------------------------+
				Info: *******************************************************************
				Info: Running Quartus II EDA Netlist Writer
				    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
				    Info: Processing started: Wed Apr 14 19:34:42 2010
				Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ADC_SEG8_DISPLAY -c ADC_SEG8_DISPLAY
				Info: Generated files "ADC_SEG8_DISPLAY.vho" and "ADC_SEG8_DISPLAY_vhd.sdo" in directory "E:/毕设/软件/ADC_SEG8_DISPLAY/simulation/modelsim/" for EDA simulation tool
				Info: Generated files "ADC_SEG8_DISPLAY.vho" and "ADC_SEG8_DISPLAY_vhd.sdo" in directory "E:/毕设/软件/ADC_SEG8_DISPLAY/timing/primetime/" for EDA timing analysis tool
				Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF
				Info: Generated PrimeTime Tcl script file E:/毕设/软件/ADC_SEG8_DISPLAY/timing/primetime/ADC_SEG8_DISPLAY_pt_vhd.tcl
				Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning
				    Info: Allocated 100 megabytes of memory during processing
				    Info: Processing ended: Wed Apr 14 19:34:43 2010
				    Info: Elapsed time: 00:00:01
				
				
							

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