开关电源的设计及仿真.rar
源代码在线查看： test buck cycle-by-cycle vm.als
.ALIASES
L_L1 L1(1=VOUT 2=N716813 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS731909@ANALOG.L.Normal(chips)
V_V7 V7(+=N716967 -=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732155@SOURCE.VDC.Normal(chips)
R_Resr Resr(1=N716523 2=VOUT ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732399@ANALOG.R.Normal(chips)
V_Vref Vref(+=N716571 -=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS731929@SOURCE.VDC.Normal(chips)
R_R31 R31(1=N717015 2=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732175@ANALOG.R.Normal(chips)
X_U10 U10(1=N716571 5=N716321 7=ERR ) CN @CHAPTER 2_1.test buck cycle-by-cycle
+VM(sch_1):INS732419@APPLICATION.AMPSIMP.Normal(chips)
C_C3 C3(1=N716321 2=N716329 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS731949@ANALOG.C.Normal(chips)
R_Rupper Rupper(1=N716321 2=VOUT ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732197@ANALOG.R.Normal(chips)
V_V8 V8(+=N716979 -=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732453@SOURCE.VDC.Normal(chips)
V_Vin Vin(+=N716505 -=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732217@SOURCE.VDC.Normal(chips)
V_Vsaw Vsaw(+=VSAW -=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS731965@SOURCE.VPULSE.Normal(chips)
R_Rlower Rlower(1=0 2=N716321 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732475@ANALOG.R.Normal(chips)
C_C2 C2(1=ERR 2=N716321 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732237@ANALOG.C.Normal(chips)
V_V10 V10(+=N717003 -=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732007@SOURCE.VDC.Normal(chips)
V_V11 V11(+=N717015 -=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732253@SOURCE.VDC.Normal(chips)
R_R2 R2(1=N7323931 2=N716321 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732495@ANALOG.R.Normal(chips)
V_V13 V13(+=N716901 -=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732029@SOURCE.VPWL.Normal(chips)
V_V9 V9(+=N716973 -=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732515@SOURCE.VDC.Normal(chips)
E_E1 E1(OUT+=N721575 OUT-=0 IN+=ERR IN-=VSAW ) CN @CHAPTER 2_1.test buck cycle-by-cycle
+VM(sch_1):INS732275@ABM.EVALUE.Normal(chips)
R_R30 R30(1=N717003 2=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732045@ANALOG.R.Normal(chips)
R_R5 R5(1=N716807 2=N716813 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732537@ANALOG.R.Normal(chips)
X_S2 S2(1=PWM 2=0 3=N716505 4=N716807 ) CN @CHAPTER 2_1.test buck cycle-by-cycle
+VM(sch_1):INS732301@BREAKOUT.Sbreak.Normal(chips)
R_R3 R3(1=N716329 2=VOUT ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732557@ANALOG.R.Normal(chips)
X_S1 S1(1=N716901 2=0 3=VOUT 4=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732331@BREAKOUT.Sbreak.Normal(chips)
C_Cout Cout(1=N716523 2=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732579@ANALOG.C.Normal(chips)
D_D1 D1(1=0 2=N716807 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732099@BREAKOUT.Dbreak.Normal(chips)
R_R22 R22(1=N716979 2=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS731867@ANALOG.R.Normal(chips)
R_R26 R26(1=N716967 2=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732119@ANALOG.R.Normal(chips)
R_R25 R25(1=N716973 2=0 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732361@ANALOG.R.Normal(chips)
R_R32 R32(1=N721575 2=PWM ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS731889@ANALOG.R.Normal(chips)
C_C4 C4(1=0 2=PWM ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732139@ANALOG.C.Normal(chips)
C_C1 C1(1=ERR 2=N7323931 ) CN @CHAPTER 2_1.test buck cycle-by-cycle VM(sch_1):INS732383@ANALOG.C.Normal(chips)
_ _(vsaw=VSAW)
_ _(err=ERR)
_ _(PWM=PWM)
_ _(vout=VOUT)
.ENDALIASES
