开关电源的设计及仿真.rar
源代码在线查看： test buck closed-loop tran vm.als
.ALIASES
C_C1 C1(1=ERR 2=N7155371 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715527@ANALOG.C.Normal(chips)
R_R26 R26(1=N711720 2=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715779@ANALOG.R.Normal(chips)
R_Resr Resr(1=N712348 2=VOUT ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715543@ANALOG.R.Normal(chips)
C_C3 C3(1=N712114 2=N712122 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715799@ANALOG.C.Normal(chips)
R_Rupper Rupper(1=N712114 2=VOUT ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715563@ANALOG.R.Normal(chips)
R_R5 R5(1=N712726 2=N712732 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715815@ANALOG.R.Normal(chips)
V_V10 V10(+=N711756 -=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715583@SOURCE.VDC.Normal(chips)
R_R31 R31(1=N711768 2=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715835@ANALOG.R.Normal(chips)
R_R2 R2(1=N7155371 2=N712114 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715605@ANALOG.R.Normal(chips)
V_V11 V11(+=N711768 -=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715857@SOURCE.VDC.Normal(chips)
V_V9 V9(+=N711726 -=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715625@SOURCE.VDC.Normal(chips)
R_R22 R22(1=N711732 2=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715385@ANALOG.R.Normal(chips)
V_V8 V8(+=N711732 -=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715879@SOURCE.VDC.Normal(chips)
R_R3 R3(1=N712122 2=VOUT ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715647@ANALOG.R.Normal(chips)
X_U14 U14(A=N712322 C=N712726 P=0 D=N712698 ) CN @CHAPTER 2_1.test buck closed-loop tran
+VM(sch_1):INS715407@PWMSWITCH.PWMVM.Normal(chips)
V_Vref Vref(+=N712414 -=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715901@SOURCE.VDC.Normal(chips)
C_Cout Cout(1=0 2=N712348 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715669@ANALOG.C.Normal(chips)
V_V7 V7(+=N711720 -=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715921@SOURCE.VDC.Normal(chips)
R_R30 R30(1=N711756 2=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715685@ANALOG.R.Normal(chips)
X_S1 S1(1=N715214 2=0 3=VOUT 4=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715441@BREAKOUT.Sbreak.Normal(chips)
E_GAIN1 GAIN1(OUT=N712698 IN=ERR ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715941@ABM.GAIN.Normal(chips)
R_R25 R25(1=N711726 2=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715471@ANALOG.R.Normal(chips)
C_C2 C2(1=ERR 2=N712114 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715957@ANALOG.C.Normal(chips)
V_V13 V13(+=N715214 -=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715973@SOURCE.VPWL.Normal(chips)
X_U10 U10(1=N712414 5=N712114 7=ERR ) CN @CHAPTER 2_1.test buck closed-loop tran
+VM(sch_1):INS715493@APPLICATION.AMPSIMP.Normal(chips)
L_L1 L1(1=VOUT 2=N712732 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715739@ANALOG.L.Normal(chips)
V_Vin Vin(+=N712322 -=0 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715989@SOURCE.VDC.Normal(chips)
R_Rlower Rlower(1=0 2=N712114 ) CN @CHAPTER 2_1.test buck closed-loop tran VM(sch_1):INS715759@ANALOG.R.Normal(chips)
_ _(err=ERR)
_ _(vout=VOUT)
.ENDALIASES
